Ripple counter circuits are a well known type of counter circuit in which each stage of the circuit clocks the next stage. (Hence the name “ripple counter”.) Because of the ripple functionality, these circuits typically operate at a slower clock rate than other digital counters. However, ripple counter circuits are also simple and require relatively little area to implement, which makes them a preferred choice in many low-speed applications.
FIG. 1 illustrates a well known ripple up counter circuit having N bits stored in flip-flops 101_0 through 101_N−1 and providing N output signals Q0 through Q(N−1). (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) Flip-flop 101_0 implements a first stage of the counter circuit, and flip-flops 101_1 through 101_N−1 form the remaining stages of the ripple counter. Each flip-flop 101_0 through 101_N−1 is reset by reset input signal RST. The complementary data output signal QB from each flip-flop provides the data input signal D for that flip-flop. Flip-flop 101_0 is clocked by clock input signal CLK, and flip-flops 101_1 through 101_N−1 are each clocked by the complementary output signal QB from the previous stage.
The circuit of FIG. 1 operates as follows and as shown in Table 1. The least significant bit Q0 changes state with every low-to-high transition on clock input signal CLK. Each succeeding bit changes state whenever the QB value of the previous stage changes from a low value to a high value.
Referring now to Table 1, the circuit is initially reset, as shown in the first line of the table. All of the Q values (Q(N−1) through Q0) are low, and all of the QB values are high. At the next rising edge of clock input signal CLK (second line), bit Q0 changes state as a result of the rising clock edge. Signal Q0 goes high, and signal QB goes low. At the next rising clock edge (third line), signal Q0 goes low again, and signal Q0B transitions from a low value to a high value, clocking flip-flop 101_1 of the next stage. Thus, signal Q1 goes high, and signal Q1B goes low. This process continues, with changing values “rippling” up the counter from the least significant to the most significant bit.
TABLE 1Change from 0 −> 1?Toggle?. . .O2O1O0. . .02BO1BO0B. . .O2BO1BO0B. . .O2O1O0000111NNN(reset)001110NNNNNY010101NNYNYY011100NNNNNY100011NYYYYY101010NNNNNY110001NNYNYY111000NNNNNY000111YYYYYY. . .. . .. . .. . .
The circuit illustrated in FIG. 1 is a ripple up counter circuit. It is clear from Table 1 that a ripple down counter circuit can be implemented in a very similar fashion, simply by providing the inverse output signals (e.g., Q0B, Q1B, Q2B . . . ).
One important attribute of a counter circuit is how easily the circuit can be tested, e.g., to verify the functionality of each bit when the circuit is included in an integrated circuit (IC). Each bit should be tested to ensure that the bit properly transitions both from a low to a high value, and from a high to a low value. The ripple counter circuit of FIG. 1 can take a long time to test, particularly when many bits are included in the counter. For example, looking at Table 1 it is clear that to cycle a 3-bit ripple counter circuit through every transition requires eight clock cycles. More generally, for an N-bit counter, the number of clock cycles required is 2**N (two to the Nth power), where N is the number of bits in the counter circuit. By adding a set capability to the reset capability shown in FIG. 1, the test time can be reduced to 2**(N−1) clock cycles. Note that for a 24-bit counter, 2**23 (over 8 million) clock cycles are still required.
One known method of reducing the test time of a ripple counter is to provide a test mode in which the counter is functionally broken up into two or more smaller counters, i.e., with shorter chains of ripple logic. FIG. 2 illustrates an N-bit ripple up counter circuit that can be tested as three smaller counters. Each stage of the counter circuit is implemented as shown in FIG. 1, except that the clock terminals of two flip-flops 101_N/3 and 101_2N/3 are driven by multiplexers 201 and 202, respectively. Each of multiplexers 201, 202 provides either the complementary data output signal QB from the previous stage (when signal TESTEN is low) or the clock input signal CLK (when signal TESTEN is high). Thus, when signal TESTEN is low, the circuit operates in the same fashion as the circuit of FIG. 1. When signal TESTEN is high, the circuit operates as three separate ripple up counters: a first counter including flip-flops 101_0 through 101_N/3−1; a second counter including flip-flops 101_N/3 through 101_2N/3−1; and a third counter including flip-flops 101_2N/3 through 101_N−1.
For a ripple up counter circuit with 24 bits, the method demonstrated in FIG. 2 reduces the test time to 2**8 or 256 clock cycles without set capability, or 2**7 or 128 clock cycles with set capability. This test time can be further reduced by adding more multiplexers and breaking the counter circuit into yet smaller pieces during testing. However, the added multiplexers both consume additional space and reduce the speed of operation for the counter circuit. Adding the set capability also requires added logic.
Another well known approach that leads to a very testable counter is to make the counter loadable, that is, to provide the capability of loading any desired value directly into the counter flip-flops. Given this capability in an up counter, for example, each bit can be tested for a high-to-low transition simply by loading an all-ones value, providing a clock pulse, and watching for all zeros on the output terminals. Similarly, each bit can be tested for a low-to-high transition by loading a value that will cause the desired transition, providing a clock pulse, and watching the output value for that bit.
FIG. 3 illustrates a known 8-bit ripple up counter circuit that is fully loadable. The circuit of FIG. 3 includes 16 reset flip-flops (D-type) 300-307 and 340-347, 15 2-to-1 multiplexers 311-317 and 320-327, nine inverters 330-337 and 352, and a logical NAND gate 351. The data is loaded serially into an 8-bit register (flip-flops 340-347), then loaded in parallel from this register into the ripple counter that includes flip-flops 300-307. The parallel load is performed via multiplexers 320-327, under control of a parallel load control signal PLOADB. To perform the load signal PLOADB must be driven low, which only occurs when test enable signal TESTEN is high and parallel load control signal PLOAD is high. Thus, parallel load control signal PLOADB is provided by logical NAND gate 351, which is driven by signals TESTEN and PLOAD. Serial reset signal SRST is generated by inverter 352 from signal TESTEN.
A first stage of the counter circuit includes flip-flop 300, multiplexer 320, inverter 330, and flip-flop 340. Flip-flop 300 has a D data input terminal D0 driven by multiplexer 320, a clock input terminal CK driven by clock input signal CLK, a reset input terminal R driven by reset input signal RST, and a data output terminal Q that provides counter output signal Q0. Data output terminal Q also drives inverter 330, which provides the “1” input to multiplexer 320. The “0” input to multiplexer 320 is the Q data output signal SQ0 from flip-flop 340. Flip-flop 340 has a data input terminal D coupled to power high VDD, a clock input terminal CK coupled to receive serial clock signal SCLK, and a reset terminal coupled to receive serial reset signal SRST.
Each of the remaining stages of the counter circuit includes a flip-flop 301-307, a first multiplexer 321-327, a second multiplexer 311-317, an inverter 331-337, and a flip-flop 341-347. Each flip-flop 301-307 has a D data input terminal D1-D7 driven by first multiplexer 321-327, a CK clock input terminal CK1-CK7 driven by second multiplexer 311-317, a reset input terminal R driven by reset input signal RST, and a data output terminal Q that provides counter output signal Q1-Q7, respectively. Each second multiplexer 311-317 has a “0” input terminal coupled to receive the clock input signal CLK and a “1” input terminal coupled to receive the output signal from inverter 330-336 of a preceding stage. Each second multiplexer 311-317 also has a select terminal coupled to receive load signal PLOADB.
Each data output terminal Q also drives inverter 331-337, which provides the “1” input to first multiplexer 321-327, respectively. The “0” input to each first multiplexer 321-327 is the Q data output signal SQ1-SQ7 from flip-flop 341-347, respectively. Each first multiplexer 321-327 has a select terminal coupled to receive load signal PLOADB. Each flip-flop 341-347 has a data input terminal D coupled to receive the data output signal Q from the corresponding flip-flop of the previous stage, a clock input terminal CK coupled to receive serial clock signal SCLK, and a reset terminal coupled to receive serial reset signal SRST.
A significant drawback of the circuit of FIG. 3 is obvious from looking at the figure, that drawback being the relatively large size of the circuit. The circuit of FIG. 3 includes a large amount of extra logic and twice as many flip-flops as the circuit of FIG. 1, for example.
Therefore, it is desirable to provide ripple counter circuits and methods having improved testability, e.g., circuits and methods that can reduce the number of clock cycles required to test each bit without adding large amounts of additional logic.